View X40435V14Z-B_1337191.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
X40430, X40431, X40434, X40435
4Kbit EEPROM
Data Sheet May 24, 2006 FN8251.1
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES * Monitoring voltages: 5V to 9V * Independent core voltage monitor * Triple voltage detection and reset assertion --Standard reset threshold settings. See selection table on page 2. --Adjust low voltage reset threshold voltages using special programming sequence --Reset signal valid to VCC = 1V --Monitor three separate voltages * Fault detection register * Selectable power-on reset timeout (0.05s, 0.2s, 0.4s, 0.8s) * Selectable watchdog timer interval (25ms, 200ms, 1.4s or off) * Debounced manual reset input * Low power CMOS --25A typical standby current, watchdog on --6A typical standby current, watchdog off * Memory security * 4Kbits of EEPROM --16 byte page write mode --5ms write cycle time (typical) * Built-in inadvertent write protection --Power-up/power-down protection circuitry --Block lock protect 0, or 1/2, of EEPROM * 400kHz 2-wire interface * 2.7V to 5.5V power supply operation * Available packages --14 Ld SOIC, TSSOP * Pb-free plus anneal available (RoHS compliant) APPLICATIONS * Communication equipment --Routers, hubs, switches --Disk arrays, network storage * Industrial systems --Process control --Intelligent instrumentation * Computer systems --Computers --Network servers
DESCRIPTION The X40430, X40431, X40434, X40435 combines power-on reset control, watchdog timer, supply voltage supervision, second and third voltage supervision, manual reset, and Block LockTM protect serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to VCC activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VTRIP1 point. RESET/RESET is active until VCC returns to proper operating level and stabilizes. A second and third voltage monitor circuit tracks the unregulated supply to provide a power fail warning or monitors different power supply voltage. Three common low voltage combinations are available. However, Intersil's unique circuits allows the threshold for either voltage monitor to be reprogrammed to meet specific system level requirements or to fine-tune the threshold for applications requiring higher precision. A manual reset input provides debounce circuitry for minimum reset component count. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The memory portion of the device is a CMOS Serial EEPROM array with Intersil's Block Lock protection. The array is internally organized as x 8. The device features a 2-wire interface and software protocol allowing operation on an I2C bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X40430, X40431, X40434, X40435
BLOCK DIAGRAM
V3MON
+ V3 Monitor Logic VTRIP3
V3FAIL
VCC or V2MON* + VTRIP2
V2MON
V2 Monitor Logic
V2FAIL
SDA WP
Data Register Command Decode Test & Control Logic
Fault Detection Register Status Register EEPROM Array
Watchdog and Reset Logic
WDO
MR
SCL
VCC
(V1MON)
+ *X40430, X40431=V2MON X40434, X40435 = VCC VCC Monitor Logic VTRIP1
Power-on, Manual Reset Low Voltage Reset Generation
RESET X40430/34 RESET X40431/35 LOWLINE
Device
Expected System Voltages
Vtrip1(V)
2.0-4.75* 4.55-4.65* 4.35-4.45* 2.95-3.05* 2.0-4.75* 4.55-4.65* 4.55-4.65* 4.55-4.65*
Vtrip2(V)
1.70-4.75 2.85-2.95 2.55-2.65 2.15-2.25 0.90-3.50* 1.25-1.35* 1.25-1.35* 0.95-1.05*
Vtrip3(V)
1.70-4.75 1.65-1.75 1.65-1.75 1.65-1.75 1.70-4.75 3.05-3.15 2.85-2.95 2.85-2.95
POR (system)
RESET = X40430 RESET = X40431 RESET = X40434 RESET = X40435
X40430, X40431 -A 5V; 3V or 3.3V; 1.8V -B 5V; 3V; 1.8V -C 3.3V; 2.5V; 1.8V X40434, X40435 -A 5V; 3.3V; 1.5V -B 5V; 3V or 3.3V; 1.5V -C 5V; 3 or 3.3V; 1.2V
*Voltage monitor requires Vcc to operate. Others are independent of Vcc.
2
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435 Ordering Information
PART NUMBER* PART MARKING MONITORED VCC RANGE VTRIP1 RANGE VTRIP2 RANGE VTRIP3 RANGE TEMP. RANGE (C) PACKAGE PKG. DWG. #
PART NUMBER WITH RESET X40430S14-C X40430S14I-C X40430V14-C X40430V14I-C X40430S14-B X40430S14Z-B (Note) X40430S14I-B X40430S14IZ-B (Note) X40430V14-B X40430V14Z-B (Note) X40430V14I-B X40430V14IZ-B (Note) X40434S14-C X40434S14I-C X40434V14-C X40434V14I-C X40434S14-B X40434S14Z-B (Note) X40434S14I-B X40434S14IZ-B (Note) X40434V14-B X40434V14Z-B (Note) X40434V14I-B X40434V14IZ-B (Note) X40434S14-A X40434S14Z-A (Note) X40434S14I-A X40434S14IZ-A (Note) X40430S C X40430S IC X4043 0VC X4043 0VIC X40430S B X40430S ZB X40430S IB X40430S ZIB X4043 0VB X40430V ZB X4043 0VIB X40430V ZIB X40434S C X40434S IC X40434V C X40434V IC X40434S B X40434S ZB X40434S IB X40434S ZIB X40434V B X40434V ZB X40434V IB X4043 4V ZIB X40434S A X40434S ZA X40434S IA X40434S ZIA 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 1.3 to 5.5 3.1V 50mV 1.3V 50mV 1.0 to 5.5 4.6V 50mV 1.0V 50mV 2.9V 50mV 1.7 to 5.5 4.4V 50mV 2.6V 50mV 1.7 to 3.6 2.9V 50mV 2.2V 50mV 1.7V 50mV 0 to 70 -40 to +85 0 to 70 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 -40 to +85 0 to 70 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 M14.173 M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 M14.173 M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free)
3
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435 Ordering Information (Continued)
PART NUMBER* X40434V14-A X40434V14Z-A (Note) X40434V14I-A X40434V14IZ-A (Note) X40430S14-A X40430S14Z-A (Note) X40430S14I-A X40430S14IZ-A (Note) X40430V14-A X40430V14Z-A (Note) X40430V14I-A PART MARKING X40434V A X40434V ZA X40434V IA X40434VZIA X40430S A X40430S ZA X40430S IA X40430S ZIA X4043 0VA X40430V ZA X4043 0VIA 1.7 to 5.5 2.9V 50mV 1.7V 50mV MONITORED VCC RANGE 1.3 to 5.5 VTRIP1 RANGE 4.6V 50mV VTRIP2 RANGE 1.3V 50mV VTRIP3 RANGE 3.1V 50mV TEMP. RANGE (C) 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 PACKAGE 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) PKG. DWG. # M14.173 M14.173 M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP Tape and Reel (4.4mm) (Pb-free) M14.173 M14.173 M14.173 M14.173
X40430V14IZ-AT1 X4043 0VZIA (Note) PART NUMBER WITH RESET X40431S14-C X40431S14I-C X40431V14-C X40431V14I-C X40431S14-B X40431S14Z-B (Note) X40431S14I-B X40431S14IZ-B (Note) X40431V14-B X40431V14Z-B (Note) X40431V14I-B X40431V14IZ-B (Note) X40435S14-C X40435S14I-C X40435V14-C X40435V14I-C X40431S C X40431S IC X40431V C X40431 IC X40431S B X40431S ZB X40431S IB X40431S ZIB X40431V B X40431V ZB X40431V IB X40431V ZIB X40435 C X40435 IC X40435 C X40435 IC 1.0 to 5.5 4.6V 50mV 1.0V 50mV 2.9V 50mV 1.7 to 5.5 4.4V 50mV 2.6V 50mV 1.7 to 3.6 2.9V 50mV 2.2V 50mV 1.7V 50mV
0 to 70 -40 to +85 0 to 70 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 -40 to +85 0 to 70 -40 to +85
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 M14.173 M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) M14.173 M14.173
4
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435 Ordering Information (Continued)
PART NUMBER* X40435S14-B X40435S14Z-B (Note) X40435S14I-B X40435S14IZ-B (Note) X40435V14-B X40435V14Z-B (Note) X40435V14I-B X40435V14IZ-B (Note) X40435S14-A X40435S14Z-A (Note) X40435S14I-A X40435S14IZ-A (Note) X40435V14-A X40435V14Z-A (Note) X40435V14I-A X40435V14IZ-A (Note) X40431S14-A X40431S14Z-A (Note) X40431S14I-A X40431S14IZ-A (Note) X40431V14-A X40431V14Z-A (Note) X40431V14I-A X40431V14IZ-A (Note) PART MARKING X40435 B X40435S ZB X40435 IB X40435S ZIB X40435 B X40435V ZB X40435 IB X40435V ZIB X40435 A X40435S ZA X40435 IA X40435S ZIA X40435 A X40435V ZA X40435 IA X40435V ZIA X40431S A X40431S ZA X40431S IA X40431S ZIA X40431V A X40431V ZA X40431V IA X40431V ZIA 1.7 to 5.5 2.9V 50mV 1.7V 50mV 3.1V 50mV MONITORED VCC RANGE 1.3 to 5.5 VTRIP1 RANGE 4.6V 50mV VTRIP2 RANGE 1.3V 50mV VTRIP3 RANGE 2.9V 50mV TEMP. RANGE (C) 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 0 to 70 0 to 70 -40 to +85 -40 to +85 PACKAGE PKG. DWG. #
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 M14.173 M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 M14.173 M14.173 M14.173
14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld SOIC (150 mil) M14.15 14 Ld SOIC (150 mil) M14.15 (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 M14.173 M14.173 M14.173
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
PIN CONFIGURATION
X40430, X40434 14 Ld SOIC, TSSOP V2FAIL V2MON LOWLINE NC MR RESET VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC WDO V3FAIL V3MON WP SCL SDA V2FAIL V2MON LOWLINE NC MR RESET VSS X40431, X40435 14 Ld SOIC, TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC WDO V3FAIL V3MON WP SCL SDA
PIN DESCRIPTION Pin 1 Function V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. The V2MON comparator is supplied by V2MON (X40430, X40431) or by the VCC input (X40434, X40435). 3 LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. 4 NC No connect. 5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain HIGH/LOW until the pin is released and for the tPURST thereafter. 6 RESET/ RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW whenRESET ever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and for tPURST thereafter. Ground 7 VSS 8 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the watchdog time out period results in WDO going active. 9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 10 WP Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has an internal pull down resistor (>10M typical). 11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a third power supply with no external components. Connect V3MON to VSS or VCC when not used. The V3MON comparator is supplied by the V3MON input. 12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and goes HIGH when V3MON exceeds VTRIP3. There is no power-up reset delay circuitry on this pin. WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog 13 WDO timer goes active. Supply Voltage 14 VCC Name V2FAIL
6
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40430, X40431, X40434, X40435 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. - It prevents the system microprocessor from starting to operate with insufficient voltage. - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPGA to download its configuration prior to initialization of the circuit. - It prevents communication to the EEPROM, greatly reducing the likelihood of data corruption on power-up. When VCC exceeds the device VTRIP1 threshold value for tPURST (selectable) the circuit releases the RESET (X40431, X40435) and RESET (X40430, X40434) pin allowing the system to begin operation. Figure 1. Connecting a Manual Reset Push-Button
X40430, X40434 System Reset RESET MR Manual Reset VCC
in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. For the X40430 and X40431 the V2FAIL signal remains active until the V2MON drops below 1V (V2MON falling). It also remains active until V2MON returns and exceeds VTRIP2. This voltage sense circuitry monitors the power supply connected to V2MON pin. If VCC = 0, V2MON can still be monitored. For the X40434 and X40435, the V2FAIL signal remains active until VCC drops below 1V and remains active until V2MON returns and exceeds VTRIP2. This sense circuitry is powered by VCC. If VCC = 0, V2MON cannot be monitored. Low Voltage V3 Monitoring The X40430, X40431, X40434, X40435 also monitors a third voltage level and asserts V3FAIL if the voltage falls below a preset minimum VTRIP3. The V3FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. The V3FAIL signal remains active until the V3MON drops below 1V (V3MON falling). It also remains active until V3MON returns and exceeds VTRIP3. This voltage sense circuitry monitors the power supply connected to V3MON pin. If VCC = 0, V3MON can still be monitored. Early Low VCC Detection (LOWLINE) This CMOS output goes LOW earlier than RESET/RESET whenever VCC falls below the VTRIP1 voltage and returns high when VCC exceeds the VTRIP1 voltage. There is no power-up delay circuitry (tPURST) on this pin.
Manual Reset By connecting a push-button directly from MR to ground, the designer adds manual system reset capability. The MR pin is LOW while the push-button is closed and RESET/RESET pin remains HIGH/LOW until the pushbutton is released and for tPURST thereafter. Low Voltage VCC (V1 Monitoring) During operation, the X40430, X40431, X40434, X40435 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP1. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP1 for tPURST. Low Voltage V2 Monitoring The X40430 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset minimum VTRIP2. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating
7
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Figure 2. Two Uses of Multiple Voltage Monitoring
VCC X40431-A 6-10V 1M 5V 3.3V 390K VCC RESET System Reset Power Fail Interrupt Unreg. Supply 5V Reg 3.0V Reg 1.8V Reg VCC
X40431-B VCC RESET V2MON V2FAIL V3MON V3FAIL
V2MON V2FAIL V3MON (1.7V) V3FAIL
System Reset
Notice: No external components required to monitor three voltages.
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX (X = 1, 2, 3) VCC/V2MON/V3MON
VP WDO
SCL
0
7
0
7
0
7
SDA A0h 00h tWC
WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. A standard read or write sequence to any slave address byte restarts the watchdog timer and prevents the WDO signal going active. A minimum sequence to reset the watchdog timer requires four microprocessor instructions namely, a Start, Clock Low, Clock High and Stop. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40430, X40431, X40434, X40435 control register (also refer to page 20).
Figure 4. Watchdog Restart
.6s SCL 1.3s
SDA Start Stop
WDT Reset
V1, V2 AND V3 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40430 is shipped with standard V1, V2 and V3 threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X40430, X40431, X40434, X40435 trip points may be adjusted. The procedure is described in the following situation, and uses the application of a high voltage control signal.
FN8251.1 May 24, 2006
8
X40430, X40431, X40434, X40435
Setting a VTRIPx Voltage (x = 1, 2, 3) There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIPx is 2.9 V and the new VTRIPx is 3.2 V, the new voltage can be stored directly into the VTRIPx cell. If however, the new setting is to be lower than the present setting, then it is necessary to "reset" the VTRIPx voltage before setting the new value. Setting a Higher VTRIPx Voltage (x = 1, 2, 3) To set a VTRIPx threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIPx threshold voltage to the corresponding input pin Vcc(V1MON), V2MON or V3MON. Then, a programming voltage (Vp) must be applied to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for VTRIP1, 09h for VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order to program VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. To check if the VTRIPX has been set, set VXMON to a value slightly greater than VTRIPX (that was previously set). Slowly ramp down VXMON and observe when the corresponding outputs (LOWLINE, V2FAIL and V3FAIL) switch. The voltage at which this occurs is the VTRIPX (actual). CASE A Now if the desired VTRIPX is greater than the VTRIPX (actual), then add the difference between VTRIPX (desired) - VTRIPX (actual) to the original VTRIPX desired. This is your new VTRIPX that should be applied to VXMON and the whole sequence should be repeated again (see Figure 5). CASE B Now if the VTRIPX (actual), is higher than the VTRIPX (desired), perform the reset sequence as described in the next section. The new VTRIPX voltage to be applied to VXMON will now be: VTRIPX (desired) - (VTRIPX (actual) - VTRIPX (desired)). Note: This operation does not corrupt the memory array. Setting a Lower VTRIPx Voltage (x = 1, 2, 3) In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be "reset" according to the procedure described below. Once VTRIPx has been "reset", then VTRIPx can be set to the desired voltage using the procedure described in "Setting a Higher VTRIPx Voltage". Resetting the VTRIPx Voltage To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for VTRIP1, 0Bh for VTRIP2, and 0Fh for VTRIP3, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. After being reset, the value of VTRIPx becomes a nominal value of 1.7V or lesser.
Notes: 1. This operation does not corrupt the memory array. 2. Set VCC 1.5(V2MON or V3MON), when setting VTRIP2 or VTRIP3 respectively.
CONTROL REGISTER The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed. The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Registers" on page 11. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, and BP. The X40430, X40431, X40434, X40435 will not acknowledge any data bytes written after the first byte is entered. The state of the Control Register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The master should supply a stop condition to be consistent with the bus protocol.
7 6 5 WD0 4 BP 3 0 2 1 0 PUP1 WD1 RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to "1" prior to a write to the Control Register.
9
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Figure 5. Sample VTRIP Reset Circuit
VP V2FAIL RESET VTRIP1 Adj. VTRIP2 Adj. Adjust 1 14 Run SCL SDA C 6 13 X4043X 2 9 7 8
Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2, 3)
VTRIPX Programming Vx = VCC, VxMON Note: X = 1, 2, 3 Let: MDE = Maximum Desired Error
No
Desired VTRIPX< Present Value YES Execute VTRIPX Reset Sequence
MDE+ Acceptable Desired Value Error Range MDE- Error = Actual - Desired
Set VX = desired VTRIPX
New VX applied = Old VX applied + | Error |
Execute Set Higher VX Sequence
New VX applied = Old VX applied - | Error |
Apply VCC and Voltage > Desired VTRIPX to VX NO Decrease VX
Execute Reset VTRIPX Sequence
Output Switches? YES Error < MDE- Actual VTRIPX Desired VTRIPX | Error | < | MDE | DONE Error > MDE+
WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address,
10
including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a "1" to the WEL bit and zeroes to the other bits of the control register.
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Once set, WEL remains set until either it is reset to 0 (by writing a "0" to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. BP: Block Protect Bits (Nonvolatile) The Block Protect Bit BP, determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bit will prevent write operations to half or none of the array. BP
0 1
Protected Addresses (Size)
None 100h - 1FFh (256 bytes)
Memory Array Lock
None Upper Half of Memory Array
- Write one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s is the BP bit and qr are the power-up bits. This operation proceeded by a start and ended with a stop bit. Since this is a nonvolatile write cycle it will take up to 10ms (max.) to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to `1' in this third step (qxys 011r) then the RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and BP bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. - A read operation occurring between any of the previous operations will not interrupt the register write operation. - The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set.
Notes: 1. tPURST is set to 200ms as factory default. 2. Watch Dog Timer bits are shipped disabled.
PUP1, PUP0: Power-up Bits (Nonvolatile) The Power-up bits, PUP1 and PUP0, determine the tPURST time delay. The nominal power-up times are shown in the following table. PUP1
0 0 1 1
PUP0
0 1 0 1
Power-on Reset Delay (tPURST)
50ms 200ms (factory setting) 400ms 800ms
FAULT DETECTION REGISTER WD1, WD0: Watchdog Timer Bits (Nonvolatile) The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time Out Period
1.4 seconds 200 milliseconds 25 milliseconds disabled (factory setting)
The Fault Detection Register (FDR) provides the user the status of what causes the system reset active. The Manual Reset Fail, Watchdog Timer Fail and Three Low Voltage Fail bits are volatile 7
LV1F
6
5
4
3
MRF
2
0
1
0
0
0
LV2F LV3F WDF
Writing to the Control Registers Changing any of the nonvolatile bits of the control and trickle registers requires the following steps: - Write a 02H to the Control Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a start and ended with a stop). - Write a 06H to the Control Register to set the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop).
11
The FDR is accessed with a special preamble in the slave byte (1011) and is located at address 0FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. There is no need to set the WEL or RWEL in the control register to access this FDR.
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA Data Stable Data Change Data Stable
At power-up, the FDR is defaulted to all "0". The system needs to initialize this register to all "1" before the actual monitoring can take place. In the event that any one of the monitored sources fail, the corresponding bit in the register will change from a "1" to a "0" to indicate the failure. At this moment, the system should perform a read to the register and note the cause of the reset. After reading the register the system should reset the register back to all "1" again. The state of the FDR can be read at any time by performing a random read at address 0FFh, using the special preamble. The FDR can be read by performing a random read at 0FFh address of the register at any time. Only one byte of data is read by the register read operation. MRF, Manual Reset Fail Bit (Volatile) The MRF bit will be set to "0" when Manual Reset input goes active. WDF, Watchdog Timer Fail Bit (Volatile) The WDF bit will be set to "0" when the WDO goes active. LV1F, Low VCC Reset Fail Bit (Volatile) The LV1F bit will be set to "0" when VCC (V1MON) falls below VTRIP1. LV2F, Low V2MON Reset Fail Bit (Volatile) The LV2F bit will be set to "0" when V2MON falls below VTRIP2. LV3F, Low V3MON Reset Fail Bit (Volatile) The LV3F bit will be set to "0" when the V3MON falls below VTRIP3. Figure 8. Valid Start and Stop Conditions
SERIAL INTERFACE Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 7. Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 8. Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 8.
SCL
SDA Start Stop
12
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 9. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for the Slave Address Byte when the Device Identifier and/or Select bits are incorrect. In the read mode, the device will transmit eight bits of data, release the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. The device will terminate further data transmissions if an acknowledge is not Figure 9. Acknowledge Response From Receiver detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Serial Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 10. A write to a protected block of memory will suppress the acknowledge bit.
SCL from Master Data Output from Transmitter
1
8
9
Data Output from Receiver Start Acknowledge
Figure 10. Byte Write Sequence
Signals from the Master SDA Bus Signals from the Slave
S t a r t
Slave Address 0 A C K
Byte Address
Data
S t o p
A C K
A C K
13
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to `0' on the same page. This means that the master can write 16 bytes to the page starting at any location on that page. If the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. Afterwards, the address counter would point to location 6 of the page that was just written. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 11 for the address, acknowledge, and data transfer sequence. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indicate the end of the master's byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 13. Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads.
Figure 11. Page Write Operation
(1 n 16) Slave Address Byte Address Data (1) Data (n) S t o p
Signals from the Master SDA Bus Signals from the Slave
S t a r t
101000
0 A C K A C K A C K A C K
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes address pointer ends here Addr = 7
5 Bytes
address =6
address 10
address n-1
14
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Current Address Read Internally the device contains an address counter that maintains the address of the last word read incremented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. See figure 15 for the address, acknowledge, and data transfer sequence. Figure 13. Acknowledge Polling Sequence
Byte Load Completed by Issuing STOP. Enter ACK Polling
Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. See Figure 16 for the address, acknowledge, and data transfer sequence. A similar operation called "Set Current Address" where the device will perform this operation if a stop is issued instead of the second start is shown in Figure 15. The device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first Data Byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition.
Issue STOP NO
Issue START
Issue Slave Address Byte (Read or Write)
Issue STOP
ACK Returned? YES High Voltage Cycle Complete. Continue Command Sequence? YES Continue Normal Read or Write Command Sequence
NO
PROCEED
The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. At the end of the address space the counter "rolls over" to address 0000h and the device continues to output data for each acknowledge received. See Figure 17 for the acknowledge and data transfer sequence.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
15
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
SERIAL DEVICE ADDRESSING Memory Address Map CR, Control Register, CR7: CR0 Address: 1FFhex FDR, Fault DetectionRegister, FDR7: FDR0 Address: 0FFhex General Purpose Memory Organization, A8:A0 Address: 000h to 1FFh General Purpose Memory Array Configuration
Memory Address A8:A0 000h 0FFh 100h 1FFh Lower 256 bytes Upper 256 bytes Block Protect Option
- last bit of the slave command byte is a R/W bit. The R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power-up condition. Operational Notes The device powers-up in the following state: - The device is in the low power standby state. - The WEL bit is set to `0'. In this state it is not possible to write to the device. - SDA pin is the input mode. - RESET/RESET Signal is active for tPURST.
Slave Address Byte Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: - a device type identifier that is always `101x'. Where x = 0 is for Array, x = 1 is for Control Register or Fault Detection Register. - next two bits are `0'. - next bit that becomes the MSB of the address. Figure 14. X40430, X40431, X40434, X40435 Addressing
Slave Byte General Purpose Memory Control Register Fault Detection Register 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 A8 R/W 1 R/W 0 R/W
Data Protection The following circuitry has been included to prevent inadvertent writes: - The WEL bit must be set to allow write operations. - The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. - A three step sequence is required before writing into the Control Register to change Watchdog Timer or Block Lock settings. - The WP pin, when held HIGH, prevents all writes to the array and all the Register.
Word Address General Purpose Memory A7 A6 A5 A4 A3 A2 A1 Control Register 1 1 1 1 1 1 1 Fault Detection Register 1 1 1 1 1 1 1
A0 1 1
Figure 15. Current Address Read Sequence
.
Signals from the Master SDA Bus Signals from the Slave
S t a r t
Slave Address
S t o p 1 A C K
101000
Data
16
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Figure 16. Random Address Read Sequence
S t a r t S t a r t
Signals from the Master SDA Bus Signals from the Slave
Slave Address
Byte Address
Slave Address
S t o p 1
101
00
0 A C K A C K
A C K
Data
Figure 17. Sequential Read Sequence
S t o p
Signals from the Master
Slave Address
A C K
A C K
A C K
SDA Bus
1 A C K
Signals from the Slave
Data (1)
Data (2)
Data (n-1)
Data (n)
(n is any integer greater than 1)
17
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial
Min.
0C -40C
Max.
70C +85C
Version
X40430, X40431 X40434, X40435
*See Ordering Info
Chip Supply Voltage
2.7V to 5.5V 2.7V to 5.5V
Monitored* Voltages
1.7V to 5.5V 1.0V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol ICC1(1) ICC2(1)
ISB1(1)(6)
Parameter Active Supply Current (VCC) Read Active Supply Current (VCC) Write
Standby Current (VCC) AC (WDT off)
Min
Typ (4)
Max 1.5 3.0
10
6
ISB2(2)(6) ILI ILO VIL(3) VIH(3) VHYS(6)
Standby Current (VCC) DC (WDT on) Input Leakage Current (SCL, MR, WP) Output Leakage Current (SDA, V2FAIL, V3FAIL, WDO, RESET) Input LOW Voltage (SDA, SCL, MR, WP) Input HIGH Voltage (SDA, SCL, MR, WP) Schmitt Trigger Input Hysteresis * Fixed input level * VCC related level Output LOW Voltage (SDA, RESET/RESET, LOWLINE, V2FAIL, V3FAIL, WDO) Output (RESET, LOWLINE) HIGH Voltage -0.5
25
30 10 10
Unit Test Conditions mA VIL = VCC x 0.1 mA VIH = VCC x 0.9, fSCL = 400kHz A VIL = VCC x 0.1 VIH = VCC x 0.9 fSCL, fSDA = 400kHz A VSDA = VSCL = VCC Others = GND or VCC A VIL = GND to VCC
A V V VSDA = GND to VCC Device is in Standby(2)
VCC x 0.3 VCC + 0.5
VCC x 0.7
0.2 .05 x VCC
V V 0.4 V IOL = 3.0mA (2.7-5.5V) IOL = 1.8mA (2.7-3.6V) IOH = -1.0mA (2.7-5.5V) IOH = -0.4mA (2.7-3.6V)
VOL VOH
VCC - 0.8 VCC - 0.4
V
18
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter VCC Supply VTRIP1(5) VCC Trip Point Voltage Range Min
2.0 4.55 4.35 2.85 Second Supply Monitor IV2 VTRIP2(5) V2MON Current V2MON Trip Point Voltage Range 1.7 0.9 2.85 2.55 2.15 1.25 0.95 tRPD2(6) IV3 VTRIP3(5) VTRIP2 to V2FAIL V3MON Current V3MON Trip Point Voltage Range 1.7 1.65 3.05 2.85 tRPD3
(6)
Typ (4)
Max
4.75
Unit
V V V V A V V V V V V V s A V V V V s
Test Conditions
4.6 4.4 2.9
4.65 4.45 2.95 15 4.75 3.5
X40430, X40431-A, X40434, X40435 X40430, X40431-B X40430, X40431-C
x40430, X40431 x40434, X40435 X40430, X40431-A X40430, X40431-B X40430, X40431-C X40434, X40435-A&B X40434, X40435-C
2.9 2.6 2.2 1.3 1.0
2.95 2.65 2.25 1.35 1.05 5 15 4.75
Third Supply Monitor
1.7 3.1 2.9
1.75 3.15 2.95 5
X40430, X40431 X40434, X40435-A X40434, X40435-B&C
VTRIP3 to V3FAIL
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) VIL Min. and VIH Max. are for reference only and are not tested. (4) At 25C, VCC = 3V (5) See ordering information for standard programming levels. For custom programmed levels, contact factory. (6) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3)
V Vref VxMON R + C VREF - tRPDX = 5s worst case Output Pin V = 100mV
CAPACITANCE Symbol COUT(1)
CIN(1)
Note:
Parameter Output Capacitance (SDA, RESET/RESET, LOWLINE, V2FAIL,V3FAIL, WDO) Input Capacitance (SCL, WP, MR)
Max 8
6
Unit pF
pF
Test Conditions VOUT = 0V
VIN = 0V
(1) This parameter is not 100% tested.
19
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR VCC = 5V
5V VCC 2.06k SDA 30pF RESET WDO 30pF 4.6k V2FAIL, V3FAIL 30pF V2MON, V3MON 4.6k
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
A.C. TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing levels Output load
N/A
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard output load
A.C. CHARACTERISTICS Symbol
fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF tSU:WP tHD:WP Cb
Note:
Parameter
SCL Clock Frequency Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid Time the bus free before start of new transmission Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time WP Setup Time WP Hold Time Capacitive load for each bus line
Min
50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 +.1Cb(1) 20 +.1Cb(1) 0.6 0
Max
400 0.9
Unit
kHz ns s s s s s s ns s s ns
300 300
ns ns s s
400
pF
(1) Cb = total capacitance of one bus line in pF.
20
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
TIMING DIAGRAMS Bus Timing
tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR
tAA SDA OUT
tDH
tBUF
WP Pin Timing
START SCL Clk 1 Slave Address Byte SDA IN tSU:WP WP tHD:WP Clk 9
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
Nonvolatile Write Cycle Timing Symbol
tWC
Note:
(1)
Parameter
Write Cycle Time
Min
Typ
5
Max
10
Unit
ms
(1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
21
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
Power Fail Timings
VTRIPX tR
[ [
VCC V2MON or V3MON
LOWLINE or V2FAIL or V3FAIL
] ]
tRPDL tRPDX
tRPDL tRPDX
tRPDL tRPDX tF
VRVALID
X = 2, 3
RESET/RESET/MR Timings
VTRIP1 VCC tPURST tRPD1 tR RESET VRVALID tF tPURST
RESET
MR
tMD tIN1
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25C, VCC = 5V) Symbol
tRPD1(2) tRPDL t LR tRPDX(2)
tPURST
Parameters
VTRIP1 to RESET/RESET (Power-down only) VTRIP1 to LOWLINE LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL] VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3) Power-on Reset delay: PUP1 = 0, PUP0 = 0 PUP1 = 0, PUP0 = 1 (factory setting) PUP1 = 1, PUP0 = 0 PUP1 = 1, PUP0 = 1 VCC, V2MON, V3MON, Fall Time VCC, V2MON, V3MON, Rise Time Reset Valid VCC MR to RESET/ RESET delay (activation only)
Min
Typ (1)
Max
5
Unit
s ns
500 5 50(2) 200 400(2) 800(2) 20 20 1 500
s ms ms ms ms mV/s mV/s V ns
tF tR VRVALID tMD
(2)
22
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25C, VCC = 5V) (CONTINUED) Symbol
tin1 tWDO Pulse width for MR Watchdog Timer Period: WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 1, WD0 = 0 WD1 = 1, WD0 = 1 (factory setting) Watchdog Reset Time Out Delay WD1 = 0, WD0 = 0 WD1 = 0, WD0 = 1 Watchdog Reset Time Out Delay WD1 = 1, WD0 = 0 Watchdog timer restart pulse width 100
Parameters
Min
5
Typ (1)
Max
Unit
s
1.4(2) 200(2) 25 OFF 200 300
s ms ms ms
tRST1 tRST2 tRSP
12.5 1
25
37.5
ms s
Notes: (1) VCC = 5V at 25C. (2) Values based on characterization data only.
Watchdog Time Out For 2-Wire Interface
Start Clockin (0 or 1) tRSP < tWDO SCL Start
SDA tRST tWDO tRST
WDO Start
WDT Restart
Minimum Sequence to Reset WDT SCL SDA
23
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435
VTRIPX Set/Reset Conditions
(VTRIPX) VCC/V2MON/V3MON
tTSU WDO tVPS
VP
tTHD
tVPH SCL 0 7 0 7 0 7
tVPO
*
SDA A0h Start *01h sets VTRIP1 *09h sets VTRIP2 *0Dh sets VTRIP3 *03h *0Bh *0Fh resets VTRIP1 resets VTRIP2 resets VTRIP3 00h tWC
* all others reserved
VTRIP1, VTRIP2, VTRIP3 Programming Specifications: VCC = 2.0 - 5.5V; Temperature = 25C Parameter
tVPS tVPH tTSU tTHD tWC tVPO VP VTRAN1 VTRAN2 VTRAN2A VTRAN3 Vtv tVPS WDO Program Voltage Hold time VTRIPX Level Setup time VTRIPX Level Hold (stable) time VTRIPX Program Cycle Program Voltage Off time before next cycle Programming Voltage VTRIP1 Set Voltage Range VTRIP2 Set Voltage Range - X40430, X40431 VTRIP2 Set to Voltage Range - X40434, X40435 VTRIP3 Set Voltage Range VTRIPX Set Voltage variation after programming (-40 to +85C). WDO Program Voltage Setup time
Description
WDO Program Voltage Setup time
Min.
10 10 10 10 10 1 15 2.0 1.7 0.9 1.7 -25 10
Max.
Unit
s s s s ms ms
18 4.75 4.75 3.5 4.75 +25
V V V V V mV s
24
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
25
FN8251.1 May 24, 2006
X40430, X40431, X40434, X40435 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 26
FN8251.1 May 24, 2006

▲Up To Search▲

Price & Availability of X40435V14Z-B

	To Download X40435V14Z-B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .